This invention relates to thin film transistors and more particularly, to amorphous silicon, thin film field effect transistors having metallic source/drain regions with low resistance.
Thin film transistor technology is now the preferred technology for use in active element addressing of large area flat panel displays A plurality of switching elements each made up of a thin film transistor are formed on an insulating substrate in a matrix configuration. The matrix of thin film transistors are used as switching elements for pixels in liquid crystal, electroluminescence and electrochromic flat panel display devices. In the manufacture of flat panel displays, the cost of silicon or quartz substrates is quite high. This is especially true for large displays having dimensions greater than 14 inches Thus, in order to reduce manufacturing costs, simple glass substrates have been investigated to replace silicon. However, the use of glass may present a problem when polysilicon is used as a semiconductor material in the thin film transistor. Typically, polysilicon requires deposition temperatures of 600.degree. C. which may adversely affect the glass to the point where it would begin to melt. For this reason, amorphous silicon is being widely researched as a semiconductor layer in the thin film transistors with glass substrates. The amorphous silicon layer is formed by plasma enhanced chemical vapor deposition techniques at temperatures of 350.degree. C. or less, which can generally be tolerated by the glass. Nevertheless, several drawbacks have developed in the fabrication of the prior art thin film amorphous silicon transistors. One of the main difficulties in this technology is the formation of low resistance metallic contacts to the intrinsic amorphous silicon region. A second problem that has arisen is with regard to the series resistance associated with the bulk amorphous silicon. The aforementioned and other drawbacks of the prior art devices will be more fully described with reference to FIGS. 1 and 2.
FIG. 1 is a cross-sectional view of an inverted gate thin film transistor 10 having a substrate 12 and a metal gate 14 disposed thereon. An insulator layer 16 is disposed on the substrate 12 and gate 14. A layer of semiconductor material 18 is disposed on the insulator layer 16. A second insulator layer 20 is disposed on the semiconductor layer 18 and source and drain electrodes 22 and 24 are deposited in vias etched in the insulator layer 20.
The thin film transistor shown in FIG. 1 operates as an inverted gate field effect transistor by applying a voltage to the gate electrode 14. The application of the voltage causes a channel, indicated at 26, to be formed between the source electrode 22 and drain electrode 24 at the interface of the insulator layer 16 and the semiconductor layer 18. In the inverted gate structure of FIG. 1, the source and drain contacts 22, 24 are spaced from the channel 26 by a distance equal to the semiconductor layer thickness, which is generally in the range of 2000 angstroms. This spacing represents a significant additional resistance on the order of several meg ohms in the transistor which adversely affects device performance. In the prior art, the formation of the source and drain electrodes within the semiconductor layer could only be accomplished with the high temperature processes of ion implantation and diffusion. As stated above, high temperatures are not desirable when using glass substrates. In addition, if amorphous silicon is used as the semiconductor material, the resulting device would not function since the high temperatures involved in the ion implantation and diffusion would drive off the included hydrogen and the properties of the amorphous silicon would be lost.
FIG. 2 shows a cross-sectional view of a non-inverted gate thin film transistor having a glass substrate 28 and a semiconductor layer 30 disposed thereon. Source and drain contacts 32 and 34 are deposited on the semiconductor layer 30 and a gate insulator layer 36 is deposited over the semiconductor layer 30 and source and drain contacts 32 and 34. A metallic gate electrode 38 is deposited on the insulator layer 36 to complete the device. Similar channel contact problems exits in the device of FIG. 2 as corner field effects inhibit contact and increase the resistance.
In addition, the fabrication of thin film FETs requires an alignment of the gate with the source and drain electrodes. As shown in FIG. 2, a portion of the gate 38 overlaps the source and drain electrodes. Critical alignment steps are necessary to ensure the gate sufficiently overlaps the source and drain electrode. This overlap is necessary in order to provide high transconductance between the source and drain electrodes. However, the source to gate and drain to gate overlaps are limited in extent to prevent the formation of large source to gate and drain to gate capacitances, which would create undesirable parasitic capacitances.
Accordingly, optimum FET performance has been achieved through stringent alignment of the metal electrode to the source and drain electrodes. This is especially true in the fabrication of a display system where small parasitics cannot be tolerated. In a practical manufacturing environment, such a stringent alignment requirement is not easily complied with. Alignment for devices formed on large glass substrates are particularly difficult as the glass tends to warp during processing so that transistors aligned on one area of the substrate will be misaligned on another area of the substrate. As a consequence, a typical manufacturing yield of a batch of thin film FETs tends to be lower than desirable.
Moreover, as with the device of FIG. 1, attempts to build devices having the source an drain formed within the semiconductor layer than encroach beneath the gate have been unsuccessful when using amorphous silicon on a glass substrate. Encroachment is effected by ion implantation by diffusion which destroys the amorphous silicon properties.